Share Email Print

Proceedings Paper

Method For Accurately Forecasting The Effects Of The "Post Exposure Bake"
Author(s): Yuichiro Yanagishita; Kazumasa Shigematsu; Kimio Yanagida
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Post Exposure Bake (PEB) is one of the simple method for minimizing the influences of reflection from a substrate to a resist film. Although various references have been made to the heating process ,its mechanism has not been fully clarified yet and it has been difficult to forecast its effects accurately. To grasp PEB effects upon the resist performance exactely ,the next two kinds of change in the development rate by this process must be measured. (1) Change by PEB in the development rate curve for the remain of photoactive compounds. (2) Smoothing by PEB of the local development rate distribution. These data can be acquired by Development Rate Monitor. The first one is translated into the sets of the fitting parameters of the development rate curve in the lithography simulator. The second one will be represented by means of the thermal diffusion model. The change (2) has significant effects upon the lithography on highly reflective substrates (silicon, aluminum etc.), for these substrates generate large amount of standing wave in a resist film. Because the smoothing effect enhances the development contrast of photoresist, PEB process contributes to improvement of the lithography on these substrates. On the contrary, for low reflective substrates (silicon-oxide etc.) which give only small amount of standing wave the effects of (1) is relatively given more weight than the smoothing effect. Because the change (1) decreases the development contrast, PEB on low-reflective layers depresses lithographic performance. This report will simulate PEB effects, compare them with experimental data and clarify the relation between PEB performance and reflection of substrates.

Paper Details

Date Published: 19 July 1989
PDF: 11 pages
Proc. SPIE 1087, Integrated Circuit Metrology, Inspection, and Process Control III, (19 July 1989); doi: 10.1117/12.953122
Show Author Affiliations
Yuichiro Yanagishita, Fujitsu Limited (Japan)
Kazumasa Shigematsu, Fujitsu Limited (Japan)
Kimio Yanagida, Fujitsu Limited (Japan)

Published in SPIE Proceedings Vol. 1087:
Integrated Circuit Metrology, Inspection, and Process Control III
Kevin M. Monahan, Editor(s)

© SPIE. Terms of Use
Back to Top