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Proceedings Paper

Defect Partitioning: A New Methodology
Author(s): Susan P. Billat; Prasanna Chitturi
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Paper Abstract

The implementation of full wafer inspection at each point in the fabrication process has resulted in a new methodology for tracking and then eliminating defects. The three-dimensional inspection, made possible by use of holography and optical spatial frequency filtering, means that a recorded defect is never out of focus. Full wafer inspection is therefore a volume, rather than an area, technology. Now, wafer inspection is not limited to the less complex topography of some levels, but includes levels such as trench, contact, via, metal, and passivation. A defect partitioning technique has been developed for the purpose of: (1) pinpointing the source of each defect and, (2) determining if the defect results in permanent damage to the circuit and subsequent yield loss. Wafers are inspected at all critical points in the process, with and without photoresist, and the defect maps are stacked. Special algorithms have been developed to process data at each level and to subtract from it defects from all previous levels. This procedure isolates the defect maps that are unique to each layer with the precise X, Y coordinates for each defect. Classified defects may be assigned a color and mapped from the printed paper report, identifying clusters as they appear in a single layer and tracking them through partitioning studies. Using this method of layer subtraction, and by using color for the study, defect clusters and individual defects can be tracked throughout the process. A variety of analysis programs will be presented including the results from partitioning studies completed with fabricated VLSI circuits.

Paper Details

Date Published: 19 July 1989
PDF: 11 pages
Proc. SPIE 1087, Integrated Circuit Metrology, Inspection, and Process Control III, (19 July 1989); doi: 10.1117/12.953094
Show Author Affiliations
Susan P. Billat, Insystems (United States)
Prasanna Chitturi, Insystems (United States)


Published in SPIE Proceedings Vol. 1087:
Integrated Circuit Metrology, Inspection, and Process Control III
Kevin M. Monahan, Editor(s)

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