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Proceedings Paper

Reduced Device Damage Using An Ozone Based Photoresist Removal Process
Author(s): Calvin Gabriel; James C. Mitchener
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Paper Abstract

With advances in new semiconductor IC manufacturing techniques and more complex process flows, the processing environment that a wafer is exposed to has become a critical issue. New CMOS process flows with shallow junction regions and thin gate oxides are susceptible to damage by free electrons and charged ionic species found in plasma processing environments. The following article presents data to quantify device damage due to various photoresist removal techniques. A dry chemical, ozone based ashing process is compared with more conventional wet chemical and plasma resist stripping methods. In this study, several ashers were compared with wet stripping and with traditional barrel ashing to quantify damage to thin gate oxides. Systems tested included two "downstream" RF plasma ashers, two "downstream" microwave plasma ashers and the non-plasma ozone ashing system. Tests were conducted to detect damage to gate oxides using CV (capacitance-voltage) and TDDB (time-dependent-dielectric-breakdown) measurements. Only the ozone asher did not cause measurable damage to 250Å gate oxides. The major source of damage appearing to be charge build up across capacitors during plasma ashing after poly etch.

Paper Details

Date Published: 30 January 1989
PDF: 7 pages
Proc. SPIE 1086, Advances in Resist Technology and Processing VI, (30 January 1989); doi: 10.1117/12.953071
Show Author Affiliations
Calvin Gabriel, VLSI Technology, Inc. (United States)
James C. Mitchener, Fusion Semiconductor Systems (United States)

Published in SPIE Proceedings Vol. 1086:
Advances in Resist Technology and Processing VI
Elsa Reichmanis, Editor(s)

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