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Proceedings Paper

Real-Time Architecture For Error-Tolerant Color Picture Compression
Author(s): Yusheng T. Tsai
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Paper Abstract

Real-time color image compression is always needed. This paper presents a practical error-tolerant compression algorithm for recording color pictures digitally on a tape and provides a real-time architecture such that the processing of picture compression is implemented in a single VLSI chip. The algorithm is based on the principle of block truncation coding (BTC). The picture is represented in Y-I-Q color space and each plane is divided into small blocks such that a reconstructed picture still contains the quality appropriate for 3R prints and keep compression efficiency. Any single channel error is restricted into a very small block of the picture and this feature of error-tolerance is important for the application of picture recording. The real-time architectures for three signal channels are working in parallel and each channel has a pipelinal architecture. This architecture also needs two 4-line input buffers with 24 bits in depth and two 96-bit output buffers. The whole architecture for both compression and decompression can be implemented with a single VLSI chip and be executed in real time. This approach provides two unique properties: error-tolerance and real-time execution, with which most other image compression algorithms have problems.

Paper Details

Date Published: 5 April 1989
PDF: 8 pages
Proc. SPIE 1075, Digital Image Processing Applications, (5 April 1989); doi: 10.1117/12.952638
Show Author Affiliations
Yusheng T. Tsai, Eastman Kodak Company (United States)

Published in SPIE Proceedings Vol. 1075:
Digital Image Processing Applications
Ying-Wei Lin; Ram Srinivasan, Editor(s)

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