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Proceedings Paper

Design and Implementation of a Cellular-Logic VME Processor Module
Author(s): Ruud Boekamp; Frans C. A. Groen; Frans A. Gerritsen; Ruud J. van Munster
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Paper Abstract

Cellular-logic (or morphological) operations such as erosion, dilation, contour extraction, propagation, skeletonization, local majority voting, and pepper-and-salt noise removal are essential tools in processing and measuring binary images. This paper describes the design and implementation of a Cellular Logic Processor module for use in VME-bus oriented image-processing systems. The Cellular-Logic Operators are implemented in a general way by table look-up, while using specialized hardware for address-generation, neighbourhood updating and bit-plane combination. The on-board memory accomodates four binary images (bitplanes) of 256 x 256 pixels each. The processor works at a 7.2 MHz pixel rate, performing a logical combination of two bitplanes, followed by a cellular-logic operation in a total of 9.2 ms.

Paper Details

Date Published: 21 April 1986
PDF: 5 pages
Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); doi: 10.1117/12.952286
Show Author Affiliations
Ruud Boekamp, Delft University of Technology (The Netherlands)
Frans C. A. Groen, Delft University of Technology (The Netherlands)
Frans A. Gerritsen, Nederlandse Philips Bedrijven B.V. (The Netherlands)
Ruud J. van Munster, Institute of Applied Physics (The Netherlands)

Published in SPIE Proceedings Vol. 0596:
Architectures and Algorithms for Digital Image Processing III
Francis J. Corbett; Howard Jay Siegel; Michael J. Duff, Editor(s)

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