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Proceedings Paper

A Bit-Sequential VLSI "Pixel-Kernel-Processor" For Image Processing
Author(s): O. R. Hinton; H.-G. Kim
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Paper Abstract

An architecture for image processing based on a "pixel-kernel-processor" approach is described in detail. The pixels are processed in raster scan order, and it is shown that many of the complexity and data communication problems of cellular-logic-arrays are avoided. By extensive use of pipelining and bit-sequential arithmetic, it is shown that a processor device is readily feasible in current NMOS or CMOS technology. The structure is flexible in that devices may be paralleled up to increase both kernel size and performance, and video throughput rates are readily attainable.

Paper Details

Date Published: 21 April 1986
PDF: 7 pages
Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); doi: 10.1117/12.952282
Show Author Affiliations
O. R. Hinton, University of Kent at Canterbury (United Kingdom)
H.-G. Kim, University of Kent at Canterbury (United Kingdom)


Published in SPIE Proceedings Vol. 0596:
Architectures and Algorithms for Digital Image Processing III
Francis J. Corbett; Howard Jay Siegel; Michael J. Duff, Editor(s)

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