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Proceedings Paper

Array Processors: New Architectures for Vision
Author(s): Barry Isenstein; Scott Israel; Robert Frisch
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Paper Abstract

Array processors are being utilized in combination with microcomputers to provide high performance sophisticated processing for vision systems. Many manufacturers of vision systems have endeavored to build proprietary array processors because an off-the-shelf solution has not been available at a reasonable cost. The ZIP 3216 array processor has overcome the obstacles that have inhibited the widespread use in vision systems through hardware and software innovations. The architecture allows for easy integration of the array processor into almost any configuration and the software enviroment allows for easy customization of algorithms and efficient programming. Details of the programming environment will be discussed with emphasis on programming examples that eliminate the need for microprogramming the array processor. The features of the hardware design that allow for optimal speed and flexible integrating and upgrading capabilites, will also be discussed.

Paper Details

Date Published: 11 December 1985
PDF: 6 pages
Proc. SPIE 0579, Intelligent Robots and Computer Vision IV, (11 December 1985); doi: 10.1117/12.950815
Show Author Affiliations
Barry Isenstein, Mercury Computer Systems, Inc (United States)
Scott Israel, Mercury Computer Systems, Inc (United States)
Robert Frisch, Mercury Computer Systems, Inc (United States)

Published in SPIE Proceedings Vol. 0579:
Intelligent Robots and Computer Vision IV
David P. Casasent, Editor(s)

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