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Proceedings Paper

Ada Model Of The VHSIC Parallel Programmable Processor For Image Processing
Author(s): Ralph Martinez; Tim Kennedy; Aaron Kam Siu
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Paper Abstract

The Honeywell Parallel Programmable Processor (PPP) set of VHSIC chips is intended to provide a flexible architecture for two dimensional real-time image processing. The chip set consists of three devices; the PPP, Sequencer, and Arithmetic Generator. In performing an analysis of the use of these devices in an image processing application, the designer must often simulate the imaging algorithm so that it fits the architecture of the VHSIC devices. In this paper we describe a macro-model of the Honeywell PPP devices written in the DoD Ada language. The Ada model for the PPP uses the concurrency features of Ada to emulate the parallel processing internal to the PPP devices. An image processing algorithm performed on two dimensional images using the Ada model are described. The Ada model is useful to understand the processing characteristics of algorithms when they are to be executed in the Honeywell PPP architecture.

Paper Details

Date Published: 4 January 1986
PDF: 5 pages
Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949709
Show Author Affiliations
Ralph Martinez, The University of Arizona (United States)
Tim Kennedy, The University of Arizona (United States)
Aaron Kam Siu, The University of Arizona (United States)

Published in SPIE Proceedings Vol. 0564:
Real-Time Signal Processing VIII
Keith Bromley; William J. Miceli, Editor(s)

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