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Proceedings Paper

Arithmetic Frequency Synthesis Using A Systolic Array
Author(s): Douglas N. Curry
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Paper Abstract

A systolic clock generator has been designed and built with 320 identical computing elements on a single VLSI chip which can provide a considerable increase in the rate at which an accumulator may be used to produce a variable frequency clock. A single Arithmetic Frequency Synthesizer (AFS) chip (with appropriate external circuitry), having the equivalent of sixteen accumulators, can provide a programmable clock at frequencies sixteen times greater than that obtainable with a single accumulator. By using up to four AFS chips in parallel, a 64 times improvement of the system output clock frequency may be obtained.

Paper Details

Date Published: 4 January 1986
PDF: 6 pages
Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949708
Show Author Affiliations
Douglas N. Curry, Xerox Corporation - Palo Alto Research Center (United States)

Published in SPIE Proceedings Vol. 0564:
Real-Time Signal Processing VIII
Keith Bromley; William J. Miceli, Editor(s)

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