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Proceedings Paper

Digital Beamforming Radar VLSI Processor
Author(s): J. Peter Costello
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Paper Abstract

A radar digital beamformer VLSI architecture is defined which provides the very high-throughput data flow in a modular failure-tolerant structure. A number of VHSIC/VLSI chip implementation approaches were evaluated and tradeoff curves are presented here. The results indicate affordability of radar elemental beamformers including large two-dimensional arrays.

Paper Details

Date Published: 4 January 1986
PDF: 7 pages
Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949705
Show Author Affiliations
J. Peter Costello, General Electric Company (United States)

Published in SPIE Proceedings Vol. 0564:
Real-Time Signal Processing VIII
Keith Bromley; William J. Miceli, Editor(s)

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