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Proceedings Paper

Extending the CMU Warp Machine with a Boundary Processor
Author(s): M. Annaratone; E. Arnould; P. K. Hsiung; H. T. Kung
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Paper Abstract

A high-performance systolic array computer called Warp has been designed by CMU and is currently under construction. The full scale machine has a systolic array of 10 or more linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). By the end of 1985 the first full scale machine will be operational. Low-level vision processing for robots and autonomous vehicles are among the first applications of the machine. This paper describes a new boundary processor to be attached to an end of the linear systolic array in Warp. Extending Warp with this boundary processor will substantially enhance the performance and applicability of the machine. The extended machine will be efficient for new application areas such as solution of linear systems of equations and adaptive signal processing.

Paper Details

Date Published: 4 January 1986
PDF: 10 pages
Proc. SPIE 0564, Real-Time Signal Processing VIII, (4 January 1986); doi: 10.1117/12.949704
Show Author Affiliations
M. Annaratone, Carnegie-Mellon University (United States)
E. Arnould, Carnegie-Mellon University (United States)
P. K. Hsiung, Carnegie-Mellon University (United States)
H. T. Kung, Carnegie-Mellon University (United States)


Published in SPIE Proceedings Vol. 0564:
Real-Time Signal Processing VIII
Keith Bromley; William J. Miceli, Editor(s)

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