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Proceedings Paper

A Pipeline Architecture For Real-Time Connected Components Labeling
Author(s): James S. J. Lee; C. Lin
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Paper Abstract

A pipeline based connected components labeling architecture is described; the algorithm (an extension of Rosenfeld et al. (1966)) and architecture were verified by software simulation. The transitive closure label equivalence process is performed by a content addressable memory. The scheme takes full advantage of the concurrent memory operations provided by content addressable memory, and performs the connected components labeling in only two pipeline frames, independent of the complexity of component shapes in the input image. The connected components labeling module can work in conjunction with the existing feature and moment extraction hardware. The pipeline based architecture allows other image processing operations to be performed in the same pipeline preceding the connected components labeling module. Thus, the connected components operations effectively take no additional operation time. This simple architecture should be low cost and easy to implement in hardware.

Paper Details

Date Published: 21 March 1989
PDF: 7 pages
Proc. SPIE 1004, Automated Inspection and High-Speed Vision Architectures II, (21 March 1989); doi: 10.1117/12.948999
Show Author Affiliations
James S. J. Lee, Boeing High Technology Center (United States)
C. Lin, Boeing High Technology Center (United States)


Published in SPIE Proceedings Vol. 1004:
Automated Inspection and High-Speed Vision Architectures II
Michael J. W. Chen, Editor(s)

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