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Proceedings Paper

CCD Focal Plane Array Analog Image Processor
Author(s): E-S. Eid; E. R. Fossum
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Paper Abstract

A focal plane array designed for real-time, general-purpose, image preprocessing is described. The analog charge-coupled device-based array operates in the charge domain and has sensing, storing, and computing capabilities. It captures the image data and performs local neighborhood operations. The array is digitally programmable and various image preprocessing tasks can be implemented. It uses a single instruction, multiple data parallel architecture with one processing element serving four pixels. It can be programmed to perform A/D conversion prior to output. The ultra-compact image processor is currently being fabricated with a 3-um, double-poly, double-metal process. The 48 X 48 pixel array is projected to achieve an internal throughput as high as 576 Mops with a 54 dB dynamic range (9-bit equivalent accuracy) and 180 um detector pitch. The total power dissipation is estimated to be 12 mW or less. The total size of the 59-pad chip is 9.4 X 9.4 mm2.

Paper Details

Date Published: 16 December 1989
PDF: 9 pages
Proc. SPIE 0977, Real-Time Signal Processing XI, (16 December 1989); doi: 10.1117/12.948581
Show Author Affiliations
E-S. Eid, Columbia University (United States)
E. R. Fossum, Columbia University (United States)

Published in SPIE Proceedings Vol. 0977:
Real-Time Signal Processing XI
J. P. Letellier, Editor(s)

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