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Proceedings Paper

The Video Analysis Transputer Array (VATA)
Author(s): Jerome J. Symanski; Keith Bromley; Thomas Henderson
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Paper Abstract

This paper presents (a) an overview of the Inmos transputer and its use in parallel arrays for image processing, (b) a functional block level description of IBM-AT-compatible boards for signal/image processing research using transputers with reconfigurable interconnection topologies, and (c) an overview of the OCCAM and C programming tools for placing parallel algorithms onto such a processor. The hard-ware consists of two custom printed-circuit boards (and two commercially available boards) within an IBM AT host. The first provides a flexible input/output interface between a general-purpose high-speed input-data bus and the transputer array. The second contains 32 transputers and 4 programmable crossbar-switch interconnection chips. Several copies of the second board can be cascaded (or even partially-unpopulated) to provide for an arbitrary number of transputer chips. Each one of these boards will perform about 128 million Whetstones or, for highly regular algorithms, a sustained 48 MFLOPS.

Paper Details

Date Published: 16 December 1989
PDF: 8 pages
Proc. SPIE 0977, Real-Time Signal Processing XI, (16 December 1989); doi: 10.1117/12.948563
Show Author Affiliations
Jerome J. Symanski, Naval Ocean Systems Center (United States)
Keith Bromley, Naval Ocean Systems Center (United States)
Thomas Henderson, Naval Ocean Systems Center (United States)

Published in SPIE Proceedings Vol. 0977:
Real-Time Signal Processing XI
J. P. Letellier, Editor(s)

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