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Proceedings Paper

Algorithm-Based Error Detection Of A Cholesky Factor Updating Systolic Array Using Cordic Processors
Author(s): S. I. Chou; Charles M. Rader
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Paper Abstract

Lincoln Laboratory has developed an architecture for a folded linear systolic array using fixed-point CORDIC processors, applicable to adaptive nulling for a radar sidelobe canceler. The algorithm implemented uses triangularization by Givens rotations to solve a least-squares problem in the voltage domain. In this paper, the implementation of an inexpensive algorithm-based error-detection scheme is proposed for this systolic array. Column average checksum encoding is intended to detect most errors caused by the failure of any single arithmetic unit. It retains or almost retains the 100% processor utilization of Lincoln Laboratory's novel design. For the case of 64 degrees of freedom, the increase in time complexity is only 3%. The increase in hardware is mainly two adders and two comparators per CORDIC processor. We believe that the small increase in cost will be amply offset by the improvement in system performance brought about by this error detection.

Paper Details

Date Published: 16 December 1989
PDF: 8 pages
Proc. SPIE 0977, Real-Time Signal Processing XI, (16 December 1989); doi: 10.1117/12.948561
Show Author Affiliations
S. I. Chou, Naval Ocean Systems Center (United States)
Charles M. Rader, MIT Lincoln Laboratory (United States)


Published in SPIE Proceedings Vol. 0977:
Real-Time Signal Processing XI
J. P. Letellier, Editor(s)

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