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Proceedings Paper

A Highly Reconfigurable Array Of Powerful Processors
Author(s): R. Cohn; H. T. Kung; O. Menzilcioglu; S. W. Song
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Paper Abstract

This paper presents a highly reconfigurable architecture for two-dimensional (2D) arrays of powerful processors. Because of its high degree of reconfigurability the architecture can provide fault tolerance with efficient array utilization and support application programs requiring different interconnection structures. The proposed 2D array incorporates a flexible interconnection network using a mechanism called virtual channels. Ideally, the interconnection mechanism of a reconfigurable array would be infinitely reliable and flexible. Our evaluation results, based on the simulation of real programs for an array of Warp processors (a powerful processor developed at Carnegie Mellon and manufactured by GE), show that we can approach this goal with a modestly complex switch design.

Paper Details

Date Published: 23 February 1988
PDF: 8 pages
Proc. SPIE 0975, Advanced Algorithms and Architectures for Signal Processing III, (23 February 1988); doi: 10.1117/12.948516
Show Author Affiliations
R. Cohn, Carnegie Mellon University (United States)
H. T. Kung, Carnegie Mellon University (United States)
O. Menzilcioglu, Carnegie Mellon University (United States)
S. W. Song, University of Sao Paulo (Brazil)


Published in SPIE Proceedings Vol. 0975:
Advanced Algorithms and Architectures for Signal Processing III
Franklin T. Luk, Editor(s)

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