Share Email Print

Proceedings Paper

Submicron MOSFET Fabrication With X-Ray Lithography
Author(s): R. P. Jaeger; M. Karnezos; H. Nakano
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

X-ray lithography has been applied in a single-layer resist process to fabricate n-channel enhancement field-effect transistors with effective channel lengths (Leff) and channel widths (Weff) as small as small as 0.9 Lim and 0.5 Lim, respectively. The yields on 3" wafers ranged from as high as 50 % for the smallest MOSFETs with Leff/Weff of 0.9/0.5 to above 90% for those with Leff/Weff of 2.2/0.5 and 0.9/1.7 without process optimization. This report outlines the mask technology and the device fabrication process. The MOSFET performance is discussed with emphasis on threshold voltage and subthreshold slope uniformity and on wafer-to-wafer variations.

Paper Details

Date Published: 20 June 1985
PDF: 10 pages
Proc. SPIE 0537, Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV, (20 June 1985); doi: 10.1117/12.947488
Show Author Affiliations
R. P. Jaeger, Hewlett Packard Laboratories (United States)
M. Karnezos, Hewlett Packard Laboratories (United States)
H. Nakano, Hewlett Packard Laboratories (United States)

Published in SPIE Proceedings Vol. 0537:
Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV
Phillip D. Blais, Editor(s)

© SPIE. Terms of Use
Back to Top