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Proceedings Paper

A Class Of Reconfiguration Schemes For Fault-Tolerant Processor Arrays
Author(s): Mengly Chean; Jose A. Fortes
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Paper Abstract

A class of reconfiguration schemes for fault-tolerant processor arrays is proposed and studied. According to these schemes, a processor array that is inoperative due to presence of faulty processors is restructured by logically "spreading" faulty processors as evenly as possible throughout the array. From the characteristics of the proposed reconfiguration schemes and the processor array structures for which they are intended, closed form expressions for processor interconnection requirements are derived and implementation issues are discussed. Next, a special case of the proposed reconfiguration schemes is studied and simulated assuming two different array structures. For one of the array structures, simulation results show that the probability of survival achieved by the reconfiguration scheme is close to 1 for up to a number of faults that equals 50% of the total number of spare processors. For a larger number of faults the probability of survival degrades rapidly. On the other hand, for the other array structure, simulation results show that the probability of survival is lower than that of the first structure when the number of faults is less than 90% of the total number of spares; it is higher otherwise.

Paper Details

Date Published: 18 July 1988
PDF: 8 pages
Proc. SPIE 0939, Hybrid Image and Signal Processing, (18 July 1988); doi: 10.1117/12.947068
Show Author Affiliations
Mengly Chean, Purdue University (United States)
Jose A. Fortes, Purdue University (United States)

Published in SPIE Proceedings Vol. 0939:
Hybrid Image and Signal Processing
David P. Casasent; Andrew G. Tescher, Editor(s)

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