Share Email Print

Proceedings Paper

Advanced Digital Video Processing Unit
Author(s): Z. Orbach; A. Hershman
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Following the development of several high-speed image processing systems, it has been acknowledged that the only way to achieve real low power and system compactness is by using customized ICs. In an effort to reduce the development cost and the turnaround time, a unique architecture has been devised to combine semicustom ICs and off-the-shelf devices. The unit is controlled by a microprocessor. The microprocessor sets the various parameters according to the desired process. The procedure itself is carried out by a miniarray processor composed of an Address Generator IC, off the shelf static RAMs, and a Data processing IC. Using advanced CMOS technology and pipeline architecture, high-speed processing is achieved while power consumption and system volum are kept very low. The paper presents the architecture of the unit along with various configurations in which it can be used, and its performance.

Paper Details

Date Published: 11 July 1985
PDF: 9 pages
Proc. SPIE 0534, Architectures and Algorithms for Digital Image Processing II, (11 July 1985); doi: 10.1117/12.946567
Show Author Affiliations
Z. Orbach, Advanced Technology Center (Israel)
A. Hershman, Advanced Technology Center (Israel)

Published in SPIE Proceedings Vol. 0534:
Architectures and Algorithms for Digital Image Processing II
Francis J. Corbett, Editor(s)

© SPIE. Terms of Use
Back to Top