Share Email Print

Proceedings Paper

0.50 µm Direct Write Gate Lithography For Selectively Doped Heterostructure Transistor Devices
Author(s): D J Resnick; D K Atwood; T Y Kuo; N J Shah; F Ren
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The AlGaAs/GaAs selectively doped heterostructure transistor (SDHT) demonstrates reduced short channel effects in comparison with conventional GaAs MESFETs since the channel of the FET is confined to a two dimensional electron gas. Very short propagation delays have been demonstrated previously for submicron direct coupled FET logic circuits'. In order to reliably produce submicron gate devices, a lift-off method for defining 0.50 pm gates in AlGaAs/GaAs SDHT circuits has been developed. The gate is defined in a tri-level resist system consisting of EBR-9 as the imaging electron beam resist, germanium as the intermediate level, and PMGI as the bottom resist. The EBR-9 was chosen for its sensi-tivity and high feature resolution. Germanium insures good adhesion to both resists, and is an excellent etch mask for the PMGI. The PMGI was selected because the resist can be chemically removed at low temperatures, making it suitable for a lift-off process. Electron beam direct writing, utilizing an EBES 1112 writing system, defines the gate pattern in the EBR-9 imaging layer of the trilevel resist. EBES III is a 20 keV, 20 MHz raster scan machine with a 0.25 μm morainal spot size. Machine throughout is approximately two 50 mm wafers/hour. A global alignment scheme references the gates to the gold metal based ohmic level pattern. Following the wet development of the imaging resist, the germanium is reactive ion etched using SF6 as the etchant gas. The PMGI is subsequently etched in an oxygen plasma. In order to facilitate the lift-off process the etch is tailored to reproducibly provide a small amount of controlled undercut in the resist. The new process is compatible with the metallization and self aligned recess etch of the SDHT technology. The methods for developing the resist, maintaining gate length, and controlling the undercut in the trilevel will be discussed. In addition, the performance of devices and circuits fabricated using this process will be discussed.

Paper Details

Date Published: 14 June 1988
PDF: 8 pages
Proc. SPIE 0923, Electron-Beam, X-Ray, and Ion Beam Technology: Submicrometer Lithographies VII, (14 June 1988); doi: 10.1117/12.945664
Show Author Affiliations
D J Resnick, AT&T Bell Laboratories (United States)
D K Atwood, AT&T Bell Laboratories (United States)
T Y Kuo, AT&T Bell Laboratories (United States)
N J Shah, AT&T Bell Laboratories (United States)
F Ren, AT&T Bell Laboratories (United States)

Published in SPIE Proceedings Vol. 0923:
Electron-Beam, X-Ray, and Ion Beam Technology: Submicrometer Lithographies VII
Arnold W. Yanof, Editor(s)

© SPIE. Terms of Use
Back to Top