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Proceedings Paper

Sub-Half Micrometer Gate Lift-Off By Three Layer Resist Process Via Electron Beam Lithography For Gallium Arsenide Monolithic Microwave Integrated Circuits (MIMICs)
Author(s): Rao M. Nagarajan; Steven D. Rask; Michael R. King; Thomas K. Yard
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Paper Abstract

A three layer resist process for gate lift-oft on Gallium Arsenide MIMICs by electron Dean and optical lithographies are described. The electron beam lithography process consists of Poly (Dimethyl Glutarimide) PMGI as tne planarizing layer, a Plasma Enhanced Chemical Vapour Deposition silicon nitride (SiN) as an intermediate barrier layer and Poly (Methyl methacrylate), PMMA, as the top imaging layer. The PivimA is exposed by Cambridge Electron beam system EBMF 6.4 at 20kev and developed in Methyl Ethyl Ketone/Iso Propyl Alcohol. The pattern is then transferred to the SiN layer by cF4/o2 plasma etcning. The SiN layer is then used as the mask to transfer the pattern to the PMGI layer by 02 kteactive Ion Etching until tne GaAS is exposed. The various processing parameters are optimized to obtain lip or overnang suitable for lift-off with 0.20μm gate dimension. After the GaAS has been recessed (to reduce the parasitic source resistance), a thick 9000Å Ti/Pt/Au gate metal is evaporated and the unwanted gate metal is lifted oft using PMGI stripper. To use the three layer resist process in optical litnograpny, the MG.'. planarizing layer and PECVD SiN layer is used along with optical pnotoresist AZ1450J as a top imaging layer. inc sofcbake, uV exposure dose (436 nm) and development time for AZ145UJ are optimized to obtain 0.5μm to 1.0μm gate dimensions. The etch parameters for the pattern transfer to SiN and tnen to PMGI layers are same as in tne above process. The process levels such as mesa, source/drain, contact and metal levels for GaAs mlivilt,s are defined by UV lithography (Karl Suss contact aligner) using single layer pnotoresist. A nign overlay accuracy is obtained by use of gold metal Dumps as registration marks for aligning tne electron Dean exposed gate to optically exposed source/drain channel. Thus a higher tnrougnput and better linewidtn control are obtained using electron beam/optical lithography tecnniques. This approach is currently used to fabricate a 0.20μm gate Metal Semiconductor Field Effect Transistors on GaAS. These results are discussed in detail.

Paper Details

Date Published: 14 June 1988
PDF: 7 pages
Proc. SPIE 0923, Electron-Beam, X-Ray, and Ion Beam Technology: Submicrometer Lithographies VII, (14 June 1988); doi: 10.1117/12.945650
Show Author Affiliations
Rao M. Nagarajan, Unisys Corporation (United States)
Steven D. Rask, Unisys Corporation (United States)
Michael R. King, Unisys Corporation (United States)
Thomas K. Yard, Unisys Corporation (United States)

Published in SPIE Proceedings Vol. 0923:
Electron-Beam, X-Ray, and Ion Beam Technology: Submicrometer Lithographies VII
Arnold W. Yanof, Editor(s)

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