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Proceedings Paper

A CCD-Based Parallel Analog Processor
Author(s): J. D. Joseph; P. C.T. Roberts; J. A. Hoschette; B. R. Hanzal; J. C. Schwanebeck
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Paper Abstract

The development of a CCD-based parallel analog processor is described. The singleinstruction, multiple-data (SIMD) architecture allows substantial throughput improvements when compared to conventional serial image processing hardware. The heart of the concept is a single-chip array of analog processing elements interconnected with a two-dimensional CCD shift register network. The same analog operation is performed on all cells simultaneously. The device shows great promise in medium resolution (100 x 100) applications (such as guided weapons and robotics) where it can be directly interfaced with a staring focal plane through bump interconnections.

Paper Details

Date Published: 8 November 1984
PDF: 4 pages
Proc. SPIE 0501, State-of-the-Art Imaging Arrays and Their Applications, (8 November 1984); doi: 10.1117/12.944668
Show Author Affiliations
J. D. Joseph, Honeywell Systems and Research Center (United States)
P. C.T. Roberts, Honeywell Systems and Research Center (United States)
J. A. Hoschette, Honeywell Systems and Research Center (United States)
B. R. Hanzal, Honeywell Systems and Research Center (United States)
J. C. Schwanebeck, Honeywell Systems and Research Center (United States)


Published in SPIE Proceedings Vol. 0501:
State-of-the-Art Imaging Arrays and Their Applications
Keith N. Prettyjohns, Editor(s)

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