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Proceedings Paper

Efficient Bit-Level, Word-Level, And Block-Level Systolic Arrays For Matrix-Matrix Multiplicationt
Author(s): A J De Groot; S R Parker; E M Johansson
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Paper Abstract

This paper investigates the mapping of matrix-matrix multiplication onto bit level, word level and block level systolic arrays. Highly efficient and regular bit level, word level and block level systolic arrays are described. Efficiencies of many block level and word level systolic arrays reported in this paper approach 100%, three times the efficiencies of systolic arrays reported previously. Bit level systolic arrays reported in this paper require less computation time than than do bit level systolic arrays reported previously and, for special matrices, require less cells. Execution times of block level systolic algorithms on a sixty-four-element multiprocessor agree with theory.

Paper Details

Date Published: 20 April 1988
PDF: 9 pages
Proc. SPIE 0880, High Speed Computing, (20 April 1988); doi: 10.1117/12.944043
Show Author Affiliations
A J De Groot, Lawrence Livermore National Laboratory (United States)
S R Parker, Lawrence Livermore National Laboratory (United States)
E M Johansson, Lawrence Livermore National Laboratory (United States)


Published in SPIE Proceedings Vol. 0880:
High Speed Computing
David P. Casasent, Editor(s)

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