Share Email Print

Proceedings Paper

A One-Third Gigaflop Systolic Linear Algebra Processor
Author(s): P. J. Kuekes; M. S. Schlansker
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

ESL is building a high performance signal processor for DARPA and the Navy which will use several systolic arrays to do linear algebra operations. These systolic arrays are all constructed from just one type of systolic integrated circuit. This systolic chip performs 32-bit floating point arithmetic at a ten megaflop rate. The chip contains all the registers needed to make it a systolic cell. All the control and registers for doing complex multiplication and addition are included in the chip. The processor contains four types of systolic arrays. The first does matrix multiplication. The second updates the Cholesky factor of a matrix from the corresponding factor of a rank-one modification of the matrix. The third array does forward and backsolves. The fourth does back-solves against many right-hand-sides. These systolic arrays have address generators which allow them to be used on many different sized problems. The detailed control for the machine is created at compile time from high level commands given by the user. Much of the hardware design effort has gone into memories and address generators which support running many different problem sizes on fixed sized arrays.

Paper Details

Date Published: 28 November 1984
PDF: 3 pages
Proc. SPIE 0495, Real-Time Signal Processing VII, (28 November 1984); doi: 10.1117/12.944019
Show Author Affiliations
P. J. Kuekes, ESL, A Subsidiary of TRW (United States)
M. S. Schlansker, ESL, A Subsidiary of TRW (United States)

Published in SPIE Proceedings Vol. 0495:
Real-Time Signal Processing VII
Keith Bromley, Editor(s)

© SPIE. Terms of Use
Back to Top