Share Email Print
cover

Proceedings Paper

High-Speed Serial Shift Registers
Author(s): John X. Przybysz; R. D. Blaugher
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

An integrated circuit chip was designed for a Josephson based shift register, and chip processing was initiated. The circuit design simulates operation at 25 GHz in the SPICE program. The transmission lines used to distribute the three-phase clock were modeled with the SUPERCOMPACT program to provide balanced, in-phase circuit drive, up to 10 GHz. Integrated circuit processing procedures have been developed to permit reactive ion etching of all seven deposited layers. The 6.25 mm square chip featured a twelve-gate, four-stage shift register fabricated with Nb/A10x/Nb Josephson junctions of 2000 A/cm critical current density.

Paper Details

Date Published: 18 May 1988
PDF: 7 pages
Proc. SPIE 0879, Sensing, Discrimination, and Signal Processing and Superconducting Materials and Intrumentation, (18 May 1988); doi: 10.1117/12.943982
Show Author Affiliations
John X. Przybysz, Westinghouse Research and Development Center (United States)
R. D. Blaugher, Westinghouse Research and Development Center (United States)


Published in SPIE Proceedings Vol. 0879:
Sensing, Discrimination, and Signal Processing and Superconducting Materials and Intrumentation
James A. Ionson; Roy Nichols, Editor(s)

© SPIE. Terms of Use
Back to Top