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Proceedings Paper

A Versatile Chip Set For Image Processing Algorithms
Author(s): M. S. Krishnan
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Paper Abstract

This paper presents a versatile chip set that can realize signal/image processing algorithms used in several important image processing applications, including template-processing, spatial filtering and image scaling. This chip set architecture is superior in versatility, programmability and modularity to several schemes proposed in the literature. The first chip, called the Template Processor, can perform a variety of template functions on a pixel stream using a set of threshold matrices that can be modified or switched in real-time as a function of the image being processed. This chip can also be used to perform data scaling and image biasing. The second chip, called the Filter/Scaler chip, can perform two major functions. The first is a transversal filter function where the number of sample points is modularly extendable and the coefficients are programmable. The second major function performed by this chip is the interpolation function. Linear or cubic B-spline interpolation algorithms can be implemented by programming the coefficients appropriately. The essential features of these two basic building block processors and their significance in template-based computations, filtering, data-scaling and half-tone applications are discussed. Structured, testable implementations of these processors in VLSI technology and extensions to higher performance systems are presented.

Paper Details

Date Published: 19 February 1988
PDF: 8 pages
Proc. SPIE 0848, Intelligent Robots and Computer Vision VI, (19 February 1988); doi: 10.1117/12.942805
Show Author Affiliations
M. S. Krishnan, AST Research Inc. (United States)

Published in SPIE Proceedings Vol. 0848:
Intelligent Robots and Computer Vision VI
David P. Casasent; Ernest L. Hall, Editor(s)

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