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Proceedings Paper

Hybrid Architecture For Real Time Image Registration
Author(s): B.Venkateswara Rao; S. V.Ravi Kumar; R. Venkateswarlu
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Paper Abstract

This paper deals with the real time implementation of an image registration algorithm, for an application onboard a flight vehicle, where there are limitations on system power and space, in addition to the processing time constraint. Two images must be registered to find the similarity between them or to find the object motion in a scene. Real time in this application means an update time of 1/30th of a second i.e., at TV frame rate. The direct method using the normalised correlation function is chosen for implementation considering both the performance and the computational complexity. A hybrid approach using dedicated hardware for computation intensive part of the algorithm and a microprocessor based subsystem for other functions is adopted as a compromise between flexibility and efficiency. To meet the time constraint parallel pipelined architecture is used. To meet the low power requirement mostly CMOS devices are used. To meet the space constraint specific integrated circuits are being planned. A specific example of implementation is given.

Paper Details

Date Published: 18 January 1988
PDF: 8 pages
Proc. SPIE 0829, Applications of Digital Image Processing X, (18 January 1988); doi: 10.1117/12.942121
Show Author Affiliations
B.Venkateswara Rao, Defence Research and Development Laboratory (India)
S. V.Ravi Kumar, Defence Research and Development Laboratory (India)
R. Venkateswarlu, Defence Research and Development Laboratory (India)


Published in SPIE Proceedings Vol. 0829:
Applications of Digital Image Processing X
Andrew G. Tescher, Editor(s)

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