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Proceedings Paper

Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays
Author(s): H. Nelis; E. Deprettere; J. Bu
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Paper Abstract

In this paper, we present a procedure to trans-form algorithms into equivalent regular algorithms. Then, starting from these regular algorithms, we show how to synthesize systolic/wavefront arrays that can be programmed to solve problems of arbitrary size. Buffer memory and control of a resulting array is regular and simple. Also, the through-put of the array is balanced with the I/O speed of the host to which it is to be attached. Methods and tools which are presented are consistent with, and embedded in our hierarchical and interactive flow graph integration system HIFI.

Paper Details

Date Published: 25 November 1987
PDF: 10 pages
Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987); doi: 10.1117/12.942041
Show Author Affiliations
H. Nelis, Delft University of Technology (The Netherlands)
E. Deprettere, Delft University of Technology (The Netherlands)
J. Bu, Delft University of Technology (The Netherlands)


Published in SPIE Proceedings Vol. 0827:
Real-Time Signal Processing X
J. P. Letellier, Editor(s)

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