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Proceedings Paper

Concurrent Error Detection In Vlsi Processor Arrays
Author(s): C.-Y.Roger Chen; Jacob A. Abraham
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Paper Abstract

This paper describes a novel technique using residue codes to detect errors (caused by either permanent or transient faults) in numerical systolic arrays concurrently with the normal operation of the system. A careful analysis of errors is used to drastically reduce the number of residue generators and checkers necessary. Undetectable errors are avoided by suitably choosing the modulo size of the residue code and by slightly modifying the implementation of the multipliers in the truncating circuits or applying few residue code checkers to the array. Error propagation in the array is analyzed in detail to ensure that an erroneous result gen-erated by any adder or multiplier will always be detected at the outputs of the arrays. VLSI implementations of dif-ferent kinds of adders and multipliers are analyzed to show that errors due to faults inside a single bit slice will always produce a detectable error at the output of the arrays. The procedure can be applied to all the processor arrays which can be derived from signal flow graphs.

Paper Details

Date Published: 21 January 1988
PDF: 10 pages
Proc. SPIE 0826, Advanced Algorithms and Architectures for Signal Processing II, (21 January 1988); doi: 10.1117/12.942034
Show Author Affiliations
C.-Y.Roger Chen, University of Illinois (United States)
Jacob A. Abraham, University of Illinois (United States)

Published in SPIE Proceedings Vol. 0826:
Advanced Algorithms and Architectures for Signal Processing II
Franklin T. Luk, Editor(s)

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