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Proceedings Paper

Survey Of High Speed Test Techniques
Author(s): Tushar Gheewala
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Paper Abstract

The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

Paper Details

Date Published: 2 February 1988
PDF: 0 pages
Proc. SPIE 0795, Characterization of Very High Speed Semiconductor Devices and Integrated Circuits, (2 February 1988); doi: 10.1117/12.940926
Show Author Affiliations
Tushar Gheewala, Unisys (United States)

Published in SPIE Proceedings Vol. 0795:
Characterization of Very High Speed Semiconductor Devices and Integrated Circuits
Ravinder K. Jain, Editor(s)

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