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Proceedings Paper

Model Based Inspection Of Integrated Circuit Patterns Using The Scanning Electron Microscope (Sem)
Author(s): Ali E. Kayaalp; Ramesh C. Jain
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Paper Abstract

In the fully automated semiconductor integrated circuit (IC) fabrication facility of the future, individual fabrication processes are expected to be controlled on-line, by intelligent systems. The current state of a process will be supplied to these systems in part by intelligent sensors/inspection systems which will observe the product after it has been processed. These systems should be fast, nondestructive, automatic, and be able to work at high spatial resolutions. This paper describes a SEM based IC pattern shape inspection system which uses the design file of the IC as the reference model. The system is intended to identify discrepancies between the shapes of patterns transferred onto the wafer and the desired pattern shapes as stored in the design file. The algorithm uses a discrete optimization approach for finding the correspondence between image and model pattern boundary points. The paper will describe the proposed approach, present some result, and will also discuss parallel implementation issues.

Paper Details

Date Published: 17 April 1987
PDF: 8 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940425
Show Author Affiliations
Ali E. Kayaalp, The University of Michigan (United States)
Ramesh C. Jain, The University of Michigan (United States)

Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)

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