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Proceedings Paper

Low Voltage Sem Metrology For Pilot Line Applications
Author(s): T. Ahmed; S-R. Chen; H. M. Naguib; T. A. Brunner; S. M. Stuber
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Paper Abstract

In this paper, we consider the application of low voltage scanning electron microscopy (SEM) to practical pilot line problems of critical dimension (CD) measurements and in-process wafer inspection of small geometry ( <2 pm) VLSI circuits . Two low voltage field emission CD measurement SEMs with automated wafer stages and computerized digital control CD systems were used. CD data from the SEM was compared with results from optical microscopy and electron probe metrology systems. Cross-calibration of CD data between the two SEMs was also analyzed using a variety of patterned layers. These included CD patterns measured after resist development and after etching of diffusion, poly Si gate, contact and metal layers in a 1.2 μm CMOS process. Examples of inprocess wafer inspection are presented. In addition, new applications of SEM metrology for sidewall spacer width and stepped contact CD measurements are demonstrated.

Paper Details

Date Published: 17 April 1987
PDF: 9 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940414
Show Author Affiliations
T. Ahmed, Xerox Microelectronics Center (United States)
S-R. Chen, Xerox Microelectronics Center (United States)
H. M. Naguib, Xerox Microelectronics Center (United States)
T. A. Brunner, Xerox Palo Alto Research Center (United States)
S. M. Stuber, Xerox Palo Alto Research Center (United States)

Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)

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