Share Email Print
cover

Proceedings Paper

Using SEM Stereo To Extract Semiconductor Wafer Pattern Topography
Author(s): Ali E. Kayaalp; Ramesh C. Jain
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In the fully automated semiconductor integrated circuit fabrication facility of the future, individual fabrication processes are expected to be controlled, on-line, by intelligent systems. These systems will adjust process parameters based on a given process specification. The current state of a process will be supplied to these systems in part by intelligent sensors/inspection systems which will observe the product after it has been processed. These systems should be fast, nondestructive, automatic, and be able to work at high resolutions. For monitoring the etching and microlithography processes, a system that can extract integrated circuit pattern (sidewall) topography will be very useful. This paper presents our work on using automatic stereo, with scanning electron microscope (SEM) secondary electron images as input, for extracting integrated circuit pattern topography. In this paper following an introduction to the concept of shape from computer stereo vision, an algorithm that has been developed for this task will be discussed. The parallel implementation of this algorithm on an NCUBE multiprocessor will be discussed next. This will be followed by a presentation of results.

Paper Details

Date Published: 17 April 1987
PDF: 9 pages
Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); doi: 10.1117/12.940407
Show Author Affiliations
Ali E. Kayaalp, The University of Michigan (United States)
Ramesh C. Jain, The University of Michigan (United States)


Published in SPIE Proceedings Vol. 0775:
Integrated Circuit Metrology, Inspection, & Process Control
Kevin M. Monahan, Editor(s)

© SPIE. Terms of Use
Back to Top