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Proceedings Paper

Design And Performance Of A 10 MIP Optoelectronic Central Processing Unit
Author(s): R. Arrathoon; S. Kozaitis
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Paper Abstract

A description of a massively parallel optoelectronic CPU is presented. Integral to the design of the device is a complex fiberoptic interconnection pattern that serves as a portion of a programmable logic array. A rudimentary instruction set for this CPU is presented, and a corresponding interconnection pattern is derived. The system architecture is examined, and a physical realization of the CPU is presented. Operating characteristics at ten million instructions per second are detailed.

Paper Details

Date Published: 11 August 1987
PDF: 6 pages
Proc. SPIE 0752, Digital Optical Computing, (11 August 1987); doi: 10.1117/12.939907
Show Author Affiliations
R. Arrathoon, Wayne State University (United States)
S. Kozaitis, Wayne State University (United States)

Published in SPIE Proceedings Vol. 0752:
Digital Optical Computing
Raymond Arrathoon, Editor(s)

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