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Proceedings Paper

Automated Defect Inspection For In-Process Semiconductor Devices
Author(s): William H Arnold; Alan L Levine
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Paper Abstract

The fabrication of very large scale integrated circuits, usually done on silicon substrates known as wafers, is a process by which successive layers of films are deposited and patterned. Photolithographic transfer of patterned images is performed fEom a master "reticle" with a step and repeat camera, with imaging Fspabilities of -2 x 108 discrete 1 elements in a single exposure of a field area of 2cm . Typical processes contain approximately 60 exposure fields per wafer level and have UP to 15 discrete levels. Each level requires its own reticle pattern. The number of devices printed on a single wafer varies but is usually between 50 and 1000 depending on the type of device and the wafer size. Even for successful processes, typically only 50-75% of available devices actually are functional at completion. Loss of these devices is primarily due to defects encountered in the processing. It is straightforward to create a first order estimate f the nominal defect density requi5ed to support such yields by using Poisson statistics. Assuming a device size of 0.5cm ' and 10 critical levels, the defect density required to give 60% die yield is given by 2: -nDoA Yield =e 1 where n = critical device levels (1) 1 + nAD A = area of device 0 Do = defect density per wafer Do = 0.13 defects/cm2 per critical level Since device killing defects can be smaller than 1.0um, the ability to discover such defects and remove the source causes of defects is critical.

Paper Details

Date Published: 17 November 1986
PDF: 14 pages
Proc. SPIE 0654, Automatic Optical Inspection, (17 November 1986); doi: 10.1117/12.938282
Show Author Affiliations
William H Arnold, VLSI Lithography Development Group (United States)
Alan L Levine, KLA Instruments Corporation (United States)


Published in SPIE Proceedings Vol. 0654:
Automatic Optical Inspection
Lionel R. Baker; H. John Caulfield, Editor(s)

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