Proceedings PaperDense Non-Binary Arithmetic With I2L Multi-Valued Logic
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In digital signal processing a great majority of repetitive operations are arithmetic in the form of sum of products. Specialized parallel arithmetic hardware such as multiplier, multiple argument adder, etc. are being developed for this application. With the availability of multivalued logic gates , it becomes feasible to implement non-binary arithmetic which leads to denser hardware. Theoretical bounds on the complexity in non-binary arithmetic are compared to binary ones. A brief description of the quaternary I2L family precedes design examples of arithmetic operators in radix 4. Single component complex arithmetic operations in balanced base 3 are mentioned. Operators in GF (4) and in the extension fields are also shown, as possible tools in number theoretic transforms N. T. T.