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Proceedings Paper

Implementation Of Real-Time Digital Signal Processing Systems
Author(s): Madihally Narasimha; Allen Peterson; Shankar Narayan
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Paper Abstract

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct imple-mentation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Paper Details

Date Published: 8 December 1978
PDF: 10 pages
Proc. SPIE 0154, Real-Time Signal Processing I, (8 December 1978); doi: 10.1117/12.938241
Show Author Affiliations
Madihally Narasimha, Stanford University (United States)
Allen Peterson, Stanford University (United States)
Shankar Narayan, Stanford University (United States)

Published in SPIE Proceedings Vol. 0154:
Real-Time Signal Processing I
T. F. Tao, Editor(s)

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