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Proceedings Paper

Design And Implementation Aspects Of A Bus-Oriented Parallel Image Processing System
Author(s): Greg C. Nicolae
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Paper Abstract

This paper describes a bus-oriented hardware architecture for the acquisition, processing and display of high-resolution two dimensional image data patterns. The system contains dedicated bipolar processors for image acquisition and display and a moderately coupled microprocessor system for image processing. Two separate asynchronous common buses are used to support high-speed data transfer and task synchronisation in the system. The design and implementation aspects of major system components, such as pixel-bus, interleaved memory modules, image processor unit and display processor are discussed in detail. Advanced design tools for modelling parallel processes, microprograming and pipelining were used throughout the design.

Paper Details

Date Published: 9 January 1984
PDF: 8 pages
Proc. SPIE 0435, Architectures and Algorithms for Digital Image Processing, (9 January 1984); doi: 10.1117/12.937000
Show Author Affiliations
Greg C. Nicolae, European Molecular Biology Laboratory (Germany)


Published in SPIE Proceedings Vol. 0435:
Architectures and Algorithms for Digital Image Processing
Per-Erik Danielsson; Andre J. Oosterlinck, Editor(s)

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