Share Email Print

Proceedings Paper

Time Integrating Digital Correlator
Author(s): Poohsan N. Tamura; Paul R. Haugen; B. Keith Betz
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper introduces "Interlaced Counter Propagating (ICP) Systolic Array", a new architecture for high speed systolic digital correlator operation. The interlaced arrangement of Multiply/Accumulate Units (MAUs) allow the processor to achieve 100% efficiency in MAU usage without need for complicated clocking scheme. It also shows a pipelined multiply and accumulate hardware combined with ICP architecture which allows the throughput to exceed the one with an array of conventional MAUs.

Paper Details

Date Published: 28 November 1983
PDF: 6 pages
Proc. SPIE 0431, Real-Time Signal Processing VI, (28 November 1983); doi: 10.1117/12.936450
Show Author Affiliations
Poohsan N. Tamura, Honeywell Corporate Technology Center (United States)
Paul R. Haugen, Honeywell Corporate Technology Center (United States)
B. Keith Betz, Honeywell Production Technology Lab. (United States)

Published in SPIE Proceedings Vol. 0431:
Real-Time Signal Processing VI
Keith Bromley, Editor(s)

© SPIE. Terms of Use
Back to Top