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Proceedings Paper

Automatic Flatness Tester for VLSI
Author(s): Toyohiko Yatagai; Shigeru Inaba; Hideki Nakano; Masane Suzuki
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Paper Abstract

A high speed automatic flatness analysis system for very large scale integrated circuit wafers is developed. By using the Fizeau interferometer a contour map of a silicon wafer is generated, which is analyzed with a digital image processing system. A special hardware system is developed, which performs basic image processing operations, including fringe peak detection, fringe thinning, fringe order labelling, local averaging and so on. Warpage and undulation of the wafer, which are represented by special indices, are estimated. The surface is not contacted at all during measurement.

Paper Details

Date Published: 15 November 1983
PDF: 10 pages
Proc. SPIE 0429, Precision Surface Metrology, (15 November 1983); doi: 10.1117/12.936350
Show Author Affiliations
Toyohiko Yatagai, University of Tsukuba (Japan)
Shigeru Inaba, SG Instrument Ltd. (Japan)
Hideki Nakano, SG Instrument Ltd. (Japan)
Masane Suzuki, Fuji Photo-Optical Co. Ltd. (Japan)


Published in SPIE Proceedings Vol. 0429:
Precision Surface Metrology
James C. Wyant, Editor(s)

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