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Proceedings Paper

Image Matching: A Method For Overlay Error Reduction
Author(s): Ronald E. Chappelow
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Paper Abstract

Many techniques aimed at reducing the magnitude of overlay error are practiced within the semiconductor industry. For example, attempts are made to manufacture masks as similar to each other as possible, and exposure tools used for successive product levels are selected to be as well-matched as possible. Although these and similar techniques have contributed to some reduction in overlay error, the degree of improvement has not been remarkable for several reasons. For example, there exist some contributing factors which are not easily brought under control, such as wafer-specific effects. Also, different masks interact with different exposure tools through a variety of mechanisms which produce a remarkable diversity of performance results.

Paper Details

Date Published: 7 November 1983
PDF: 7 pages
Proc. SPIE 0394, Optical Microlithography II: Technology for the 1980s, (7 November 1983); doi: 10.1117/12.935124
Show Author Affiliations
Ronald E. Chappelow, IBM General Technology Division (United States)


Published in SPIE Proceedings Vol. 0394:
Optical Microlithography II: Technology for the 1980s
Harry L. Stover, Editor(s)

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