Share Email Print

Proceedings Paper

Performance Analysis Of Systolic Array Architectures
Author(s): J. A. Bannister; J. B. Clary
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper we briefly describe the systolic array architecture. We discuss performance issues that arise in the evaluation of systolic array architectures. We review the fundamental concepts of Petri nets and consider their suitability as a tool for the modeling and analysis of systolic array architectures. We review known results concerning the use of timed decision-free Petri nets for performance evaluation of computing systems. We propose a new class of Petri nets (called coherent safety nets) that appear to be useful for performance evaluation of pipelined signal processing architectures. These techniques are applied to systolic array architectures.

Paper Details

Date Published: 28 December 1982
PDF: 9 pages
Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); doi: 10.1117/12.933722
Show Author Affiliations
J. A. Bannister, Research Triangle Institute (United States)
J. B. Clary, Research Triangle Institute (United States)

Published in SPIE Proceedings Vol. 0341:
Real-Time Signal Processing V
Joel Trimble, Editor(s)

© SPIE. Terms of Use
Back to Top