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Proceedings Paper

Configurable,Highly Parallel (CHiP) Approach For Signal Processing Applications
Author(s): Lawrence Snyder
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Paper Abstract

Between the conception of a real time signal processor and its functional, VLSI realization there is an enormous amount of effort devoted to designing, revising, optimizing and testing. Since the process is cumulative -- later work builds on previous work -- and since the activity becomes progressively more detailed, more constrained and more exacting, it follows that the global design parameters should be fully explored. Global design decisions, when correct, can have a greater effect on performance than many local optimiza-tions. When the decisions are wrong, they can cause continual difficulty. Accordingly, we propose a design methodology based on the Configurable, Highly Parallel (CHiP) architecture family1 that focuses on exploring global design parameters and is especially well suited to the VLSI implementation of signal processing systems.

Paper Details

Date Published: 28 December 1982
PDF: 9 pages
Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); doi: 10.1117/12.933690
Show Author Affiliations
Lawrence Snyder, Purdue University (United States)


Published in SPIE Proceedings Vol. 0341:
Real-Time Signal Processing V
Joel Trimble, Editor(s)

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