Share Email Print
cover

Proceedings Paper

Progress On A Systolic Processor Implementation
Author(s): J. J. Symanski
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Parallel algorithms using systolic and wavefront processors have been proposed for a number of matrix operations important for signal processing; namely, matrix-vector multiplication, matrix multiplication/addition, linear equation solution, least squares solution via orthogonal triangular factorization, and singular value decomposition. In principle, such systolic and wavefront processors should greatly facilitate the application of VLSI/VHSIC technology to real-time signal processing by providing modular parallelism and regularity of design while requiring only local interconnects and simple timing. In order to validate proposed architectures and algorithms, a two-dimensional systolic array testbed has been designed and fabricated. The array has programmable processing elements, is dynamically reconfigurable, and will perform 16-bit and 32-bit integer and 32-bit floating point computations. The array will be used to test and evaluate algorithms and data paths for future implementation in VLSI/VHSIC technology. This paper gives a brief system overview, a description of the array hardware, and an explanation of control and data paths in the array. The software system and a matrix multiplication operation are also presented.

Paper Details

Date Published: 28 December 1982
PDF: 6 pages
Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); doi: 10.1117/12.933689
Show Author Affiliations
J. J. Symanski, Naval Ocean Systems Center (United States)


Published in SPIE Proceedings Vol. 0341:
Real-Time Signal Processing V
Joel Trimble, Editor(s)

© SPIE. Terms of Use
Back to Top