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Proceedings Paper

Temperature and Chemical Vapor Deposition (CVD) film effects on wafer flatness
Author(s): Peter Gise
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Paper Abstract

The dependency of wafer flatness on high temperature and Chemical Vapor Deposition (CVD) processes has been quantified for a 400 gate array bipolar process. Experimental data is presented which describes wafer flatness variations at six critical front-end process steps.

Paper Details

Date Published: 15 October 1982
PDF: 4 pages
Proc. SPIE 0342, Integrated Circuit Metrology I, (15 October 1982); doi: 10.1117/12.933684
Show Author Affiliations
Peter Gise, Tencor Instruments (United States)

Published in SPIE Proceedings Vol. 0342:
Integrated Circuit Metrology I
Diana Nyyssonen, Editor(s)

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