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Proceedings Paper

Intralevel Hybrid Resist Process With Submicron Capability
Author(s): J. N. Helbert; P. A. Seese; A. J. Gonzales; C. C. Walker
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Paper Abstract

A hybrid lithographic process, utilizing both e-beam and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the < 3.0 micron geometries and optical exposure of the larger sized patterns, both sets of images are developed in a single development. Using this process, working CMOS devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 micron. The effect of E-beam dosage upon the submicron gate critical dimensions has been determined as well as other processing characteristics.

Paper Details

Date Published: 30 June 1982
PDF: 8 pages
Proc. SPIE 0333, Submicron Lithography I, (30 June 1982); doi: 10.1117/12.933408
Show Author Affiliations
J. N. Helbert, Motorola, Inc. (United States)
P. A. Seese, Motorola, Inc. (United States)
A. J. Gonzales, Motorola, Inc. (United States)
C. C. Walker, Motorola, Inc. (United States)


Published in SPIE Proceedings Vol. 0333:
Submicron Lithography I
Phillip D. Blais, Editor(s)

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