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Proceedings Paper

Experimental Distributed Microprocessor Implementation With A Shared Memory Communications And Control Medium
Author(s): Richard S. Mejzak
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Paper Abstract

An experimental distributed microcomputer concept has been developed, implemented, and is currently operational at the Naval Air Development Center as a vehicle to investigate distributed processing concepts with respect to replacing larger computers with networks of microprocessors at the subsystem or node level. Major benefits being exploited include increased performance, flexibility, system availability, and survivability, by use of multiple processing elements with reduced cost, size, weight and power consumption. This paper concentrates on defining the distributed processing concept in terms of control primitives, variables, and structures and their use in performing a decomposed DFT (Discrete Fourier Transform) application function on a laboratory model. The DFT was chosen as an experimental application to investigate distributed processing concepts because of its highly regular and decomposable structure for concurrent execution. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common data base by employing control primitives. Access to selected areas within the common data base is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks, are also described.

Paper Details

Date Published: 30 July 1982
PDF: 8 pages
Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); doi: 10.1117/12.932534
Show Author Affiliations
Richard S. Mejzak, Naval Air Development Center (United States)

Published in SPIE Proceedings Vol. 0298:
Real-Time Signal Processing IV
Tien F. Tao, Editor(s)

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