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Proceedings Paper

Microprogrammable High-Speed Bit Slice Image Processor
Author(s): Paul E. Thomas; Robert D. Glass
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Paper Abstract

The problem of real time image processing for an Autonomous Acquisition system required the development of a special purpose high speed processor. Commercially available bit slice components were selected for the basic computational structure for speed and versatility. The processor's basic architecture is dynamically alterable into either a serial or pipelined configuration achieving higher speed than either architecture alone could provide. The high speed afforded by this structure is further enhanced by the availability of eight parallel paths allowing a maximum throughput in excess of 40 million operations per second. The algorithms which were implemented for this application include: Sobel edge, shape/connectivity, laplacian, histogram flattening and compression, a sophisticated peak detection scheme, and a "destreaking" function. Being microprogrammable, the processor will allow the implementation of additional algorithms for alter-native applications. Ensuing discussion develops the overall architecture from a functional point of view illustrating the parallelism in the architectural design which allowed the efficient implementation of this general class of algorithms.

Paper Details

Date Published: 30 July 1982
PDF: 10 pages
Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); doi: 10.1117/12.932525
Show Author Affiliations
Paul E. Thomas, Texas Instruments Incorporated (United States)
Robert D. Glass, Texas Instruments Incorporated (United States)

Published in SPIE Proceedings Vol. 0298:
Real-Time Signal Processing IV
Tien F. Tao, Editor(s)

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