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Proceedings Paper

Systolic Array Processor Implementation
Author(s): J. J. Symanski
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Paper Abstract

A combination of systolic array processing techniques and VLSI fabrication promises to increase signal-processing capabilities by a factor of 100 or more. To achieve a timely marriage of algorithms and hardware, both must be developed concurrently. This article describes the hardware for a programmable, reconfigurable systolic array testbed, implemented with presently available integrated circuits and capable of 32-bit floating-point arithmetic. While this hardware presently requires a small printed circuit board for each processing element, in a few years one or two custom VLSI chips could be used instead, yielding a smaller, faster systolic array processor. This testbed will aid in the evaluation of the many parameters which will have to be optimized in order to design these custom chips.

Paper Details

Date Published: 30 July 1982
PDF: 6 pages
Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); doi: 10.1117/12.932508
Show Author Affiliations
J. J. Symanski, Naval Ocean Systems Center (United States)

Published in SPIE Proceedings Vol. 0298:
Real-Time Signal Processing IV
Tien F. Tao, Editor(s)

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