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Proceedings Paper

Plasma Etching 1μ Phosphorous-Doped Polysilicon Geometries At 30 Kilocycles
Author(s): R. F. Sarkozy
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Paper Abstract

In response to the need for moderate cost, totally dedicated plasma etch systems a Technics Planar Etch II plasma reactor was evaluated for the etching of micron-range geometries in 5000Å of polysilicon, phosphorous doped to 25-30Ω /0. Initial characterization included the use of a vacuum throttle in conjunction with different vacuum pumps and wafer support mechanisms to determine the most optimum gas flow conditions for uniform clearing of un-patterned wafers. A variety of gases were then employed for the etching of one, two and three micron lines and spaces using KTI Type II positive photoresist in all applications. Each etchant was operated at various pressures and RF power levels to determine absolute etch rates and sensitivities of rates to power and pressure fluctuations. Underlying oxide etch rate, rate of photoresist attack, uniformity in clearing, etched-edge profile, degree of undercut and cleanliness of exposed surfaces following etch were all monitored. It was concluded that none of the etchant gases utilized in itself lead to a set of conditions adequate for maintaining one micron geometries with no loss of underlying oxide, but rather a dual gas sequential operation was established which satisfies all requirements by utilizing an initial gas that etches uniformly with minimal undercut followed by a second etchant for clean, uniform clearing with no attack of the underlying gate oxide. The Technics Planar Etch II is conducive to etching 111 geometries in 5000 Å polysilicon films on a routine basis. Batch size is not large, eight 2" wafers/run, but the system is in a price range compatible with multi-unit, dedicated installations.

Paper Details

Date Published: 28 July 1981
PDF: 8 pages
Proc. SPIE 0275, Semiconductor Microlithography VI, (28 July 1981); doi: 10.1117/12.931893
Show Author Affiliations
R. F. Sarkozy, Hughes Aircraft Company (United States)


Published in SPIE Proceedings Vol. 0275:
Semiconductor Microlithography VI
James W. Dey, Editor(s)

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